Array device with switching circuits bootstrap capacitors

ABSTRACT

An array device has switching circuits in each pixel for selectively routing one of at least two inputs to a pixel element. Switching transistors are connected between a respective one of the at least two inputs and the pixel element. The timing of the operation of the switching transistors is determined in dependence on the data waveform of at least one of the inputs, and a capacitive connection is provided between the gate of at least one of the switching transistors and an output of the switching transistor. This enables a reduction in the data voltage range which is required to ensure that the switching transistors switch correctly, by using a bootstrapping technique. In particular, by controlling the timing of application of the data signals for switching on or off the switching transistors, the voltage levels of at least one of the input signals can be used to provide capacitive coupling through the respective switching transistor onto the bootstrapping capacitor.

This invention relates to switching circuits for use in array devices,particularly but not exclusively for use in pixels of active matrixdisplay devices.

Active matrix displays typically comprise an array of pixels arranged inrows and columns. Each row of pixels shares a row conductor whichconnects to the gates of the thin film transistors of the pixels in therow. Each column of pixels shares a column conductor, to which pixeldrive signals are provided. The signal on the row conductor determineswhether the transistor is turned on or off, and when the transistor isturned on, by a high voltage pulse on the row conductor, a signal fromthe column conductor is allowed to pass on to an area of liquid crystalmaterial (or other capacitive display cell), thereby altering the lighttransmission characteristics of the material.

It is well known to provide an additional storage capacitor as part ofthe pixel configuration to enable a voltage to be maintained on theliquid crystal material even after removal of the row electrode pulse.

The frame (field) period for active matrix display devices requires arow of pixels to be addressed in a short period of time, and this inturn imposes a requirement on the current driving capabilities of thetransistor in order to charge or discharge the liquid crystal materialto the desired voltage level. In order to meet these currentrequirements, the gate voltage supplied to the thin film transistorneeds large voltage swings. For example, in a display using lowtemperature polysilicon transistors, the minimum row drive voltage maybe around −2 Volts and the maximum around 15 Volts. This ensures thetransistor is biased sufficiently to provide the required source-draincurrent to charge or discharge the liquid crystal material sufficientlyrapidly.

The requirement for large voltage swings in the row conductors requiresthe row driver circuitry to be implemented using high voltagecomponents. It also results in relatively high power consumption.

The use of digital data to control the brightness of pixels within anactive matrix display is also of increasing interest. The integration ofdynamic memory within the pixels of active matrix displays has also beenproposed, in which a digital data value for each pixel is stored in thepixel. Digital data supplied to or stored within the pixels of thedisplay can then be used to select one of a number of different signalvoltage waveforms. The selected waveform can then be used eitherdirectly or indirectly to drive the display element, for example theliquid crystal pixel element in the case of an active matrix LCD.

FIG. 1 shows one possible arrangement which allows one of two signalvoltage waveforms to be connected to the output of the circuit dependingon the state of the data voltage input. When used to route signal to adisplay element, one of these signals may cause the display element toswitch into a dark state while the other may switch the display elementinto a light state. In a practical circuit, the switches are replaced bythin film transistors.

The area which is available for the circuits within the pixels of adisplay is limited by the dimensions of the pixel and, in the case of atransmissive display, the need to minimise the area of the pixel wherethe passage of light through the display is obscured by circuitry. Anexample of a switching circuit which minimises the number of transistorsrequired is shown in FIG. 2. The output signal can be connected directlyto the liquid crystal display element.

In this circuit, the switch connected to signal voltage 1 is implementedas an n-type TFT and the switch connected to signal voltage 2 isimplemented as a p-type TFT. The complementary behaviour of the n-typeand p-type devices means that with appropriate data voltage levels thecircuit can be switched between two states. In one state, the n-typedevice is conducting and the p-type device is non-conducting, and in theother state the n-type device is non-conducting and the p-type device isconducting.

In order to illustrate the operation of the this circuit, we canconsider two examples of the drive voltage waveforms which might beapplied to the circuit and the data voltage levels that are required toswitch the transistors between the two states.

A first example of possible voltage waveforms in shown in FIG. 3. Inthis example it is assumed that an alternating voltage waveform isapplied to the input signal 1. This waveform switches between twovoltages levels, 0V and V_(DR). A constant voltage equal to 0.5V_(DR) isapplied to the input signal 2. The voltage applied to the data voltageinput is initially at a low level, V_(DL), and then switches to a highlevel, V_(DH). When the data voltage is low, signal 2 is transferred tothe output terminal of the circuit. When the data voltage is high,signal 1 is transferred to the output terminal of the circuit. Theconditions which determine the maximum allowable value of V_(DL) and theminimum allowable value of V_(DH) are summarised in Table 1 below. TABLE1 Data Required Equation for Values for Required volt- Conditions forrequired data specified data age TFT switching voltages conditionsvoltage V_(DH) n-type TFT on V_(DH) ≧ V_(DR) + V_(non) ≧13 V 13 V p-typeTFT off V_(DH) ≧ 0.5 V_(DR) − V_(poff) ≧4.5 V V_(DL) n-type TFT offV_(DL) ≦ 0 − V_(noff) ≦0 V  0 V p-type TFT on V_(DL) ≦ 0.5 V_(DR) +V_(pon) ≦0.5 VIn this table, V_(non) is the gate-source voltage on the n-type TFTrequired to make the device sufficiently conducting, V_(noff) is thegate-source voltage on the n-type TFT required to make the devicesufficiently non-conducting. V_(pon) and V_(poff) are the equivalentparameters for the p-type TFT. The data voltage levels have beencalculated for the condition when V_(non)=4V, V_(pon)=−4V, V_(noff)=0V,V_(poff)=0V, V_(DR)=9V. These values are typical of those that would berequired for low temperature poly-Si TFTs and a twisted nematic liquidcrystal display element. The minimum value of the high level datavoltage is determined by the need to ensure that the n-type TFT remainsconducting when the voltage applied to the signal 1 input is at itshighest level. The maximum low level data voltage is determined by theneed to ensure that the n-type TFT remains in the non-conducting stateeven when the voltage applied to the signal 1 input is at its lowestlevel. The amplitude of the data voltage that is required is large,greater than or equal to 13V. Such a high value is undesirable as itwill increase the power consumption of the display.

A second example of possible waveforms is shown in FIG. 4. In thisexample, complementary alternating voltage waveforms are applied to thetwo signal inputs of the circuit. These waveforms may be appropriate forthe so-called common electrode drive scheme, in which an alternatingvoltage is applied to the common electrode of the display. Thus, signal1 may be the signal required to drive the pixel to a bright state, andsignal 2 may be the signal required to drive the pixel to a dark state(as will be explained further below). The data voltage is again steppedfrom a low level to a high level and the output signal is equal tosignal 2 when the data voltage is low, and signal 1 when the datavoltage is high. The conditions which define the required value of datavoltage are indicated in Table 2. The values of V_(non), V_(noff),V_(pon) and V_(poff) are the same as in the first example and V_(DR) hasa value of 4.5V. TABLE 2 Data Required Equation for Values for Requiredvolt- Conditions for required data specified data age TFT switchingvoltages conditions voltage V_(DH) n-type TFT on V_(DH) ≧ V_(DR) +V_(non) ≧8.5 V 8.5 V p-type TFT off V_(DH) ≧ V_(DR) − V_(poff) ≧4.5 VV_(DL) n-type TFT off V_(DL) ≦ 0 − V_(noff) ≦0 V  −4 V p-type TFT onV_(DL) ≦ 0 + V_(pon) ≦−4 V

The amplitude of the data voltage that is required is determined by thevoltages needed to turn on either the n-type or the p-type TFT. Theminimum high level of the data voltage is that which is required to turnthe n-type device on when signal 1 is at its maximum level. The maximumlow level of the data voltage is that required to turn on the p-typedevice when signal 2 is at its minimum voltage level. The required datavoltage amplitude is again relatively large, greater than or equal to12.5V.

If the output signal of the circuit is being used to drive a liquidcrystal display element, then the common electrode of the display wouldbe carry an alternating signal with an amplitude and phase equal to thatof signal 2, but with an adjusted dc voltage level. The voltageappearing across the display element is then derived from the differencebetween the output signal of the switching circuit and signal 2. Thisvoltage would have a peak to peak value of zero when the data voltage islow and 2V_(DR) when the data voltage is high.

If the swing in the data voltage could be reduced, this would enable areduction in power consumption. This may, for example, be appropriatefor a low power stand-by mode.

According to the invention, there is provided a device comprising anarray of pixels, each pixel including a pixel element and beingassociated with a switching circuit, wherein the switching circuit isfor selectively routing one of at least two inputs to the pixel element,comprising at least first and second switching transistors connectedbetween a respective one of the at least two inputs and the pixelelement, wherein each switching transistor is controlled by a datasignal applied to the gate of the transistor, wherein the data signalfor each switching transistor is routed to the gate of the switchingtransistor with predetermined timing determined in dependence on thedata waveform of at least one of the inputs, and wherein a capacitiveconnection is provided between the gate of at least one of the switchingtransistors and an output of the switching transistor.

The invention enables a reduction in the data voltage range which isrequired to ensure that the switching transistors switch correctly, byusing a bootstrapping technique. In particular, by controlling thetiming of application of the data signals for switching on or off theswitching transistors, the voltage levels of at least one of the inputsignals can be used to provide capacitive coupling through therespective switching transistor onto the bootstrapping capacitor (the“capacitive connection”).

The term “connected between” an input and an output in connection with aswitch is not intended to indicate direct connection of the output ofthe switch to the output, merely that the output of the switch is inturn coupled to the output, whether directly or through other switchesor capacitive connections. Indeed, the output is eventually the pixelelement, as the switching circuit is for routing one of a number ofsignals to the pixel element, but there are other components between theswitching transistors and the pixel element.

The array device of the invention can have the switching circuitsintegrated into each pixel, for selectively routing one of at least twoinputs to the pixel element. The switching circuits may, however, bepartially provided in peripheral address circuitry instead of purelyintegrated into the pixel area, or the switching circuit may be providedentirely in the address circuitry.

The data signal for each switching transistor can be routed to the gateof the switching transistor by a transfer switch which controls thetiming of application of the data signal for each switching transistor,and wherein a capacitive connection is provided between the gate of eachswitching transistor and the output of each switching transistor. The(or each) transfer switch allows the transistor gates to float afterapplication of the data signal.

A capacitive connection is for example provided between the gate of eachswitching transistor and a common output of the switching circuit.

The gates of the first and second switching transistors may be connectedtogether and the capacitive connection comprises a capacitor connectedbetween the gates and the common output. In this way, the bootstrappingcapacitor can be shared between the two inputs. The first switchingtransistor can be an n-type transistor and the second switchingtransistor can be a p-type transistor. This enables a single data signalto be applied to the gates of both switching transistors tosimultaneously switch one transistor on and the other off, with areduced voltage swing between the on and off voltage levels of the datasignal.

Instead, the capacitive connection may comprise a respective capacitorconnected between the gate of each switching transistor and the commonoutput. Each transistor may then be individually switchable.

The circuit may comprising n inputs, where n is greater than 2, andcomprise first to nth switching transistors connected between arespective one of the n inputs and the pixel element, and wherein thedata signals for each switching transistor are selected such that anindividual one of the switching transistors is turned on to route therespective input to the pixel element. This provides a one-of-nselection circuit. In this arrangement, some switching transistors canbe n-type and others p-type, or they may all be the same.

The circuit may comprise n inputs, but with first to nth switchingtransistors connected between a respective one of the n inputs and oneof two intermediate outputs, and wherein the data signals for eachswitching transistor are selected such that half of the switchingtransistors are turned on to route a first selected input to oneintermediate output and to route a second selected input to the otherintermediate output. This arrangement provides two channels in parallel,with an input selected for each channel. This can form the buildingblock for a selector circuit using a binary word as the control signal.For example, a further switching circuit can selectively route one ofthe intermediate outputs inputs to the common output, namely the pixel,and this can provide a one of four selector controlled by a two bitword.

The device of the invention can be an active matrix display device. Thedisplay device may comprise an array of pixels, each pixel comprising:

-   -   the switching circuit of the invention for routing one of (at        least) two voltage drive levels to a common output;    -   a first selection switch between the common output and the        liquid crystal cell of the pixel; and    -   a second selection switch between an analogue pixel data line        and the liquid crystal cell of the pixel.

In this arrangement, the switching circuit can select between bright anddark, for a low power mode of operation in which low voltages areneeded. This mode of operation is selected by the first selectionswitch. However, the display can also be used in a normal analogue mode,and this mode is selected by the second selection switch.

The control signal for selecting which one of the two voltage drivelevels is to be routed to the common output can be provided on theanalogue pixel data line, which is thus shared between the two modes ofoperation.

The invention also provides a method of routing one of at least twoinputs to a pixel element within a pixel of a device comprising an arrayof pixels, the method comprising:

-   -   applying data signals to the gates of at least first and second        switching transistors connected between a respective one of the        at least two inputs and the pixel element to turn on a selected        one of the first and second switching transistors and turn off        the other of the first and second switching transistor, thereby        routing the respective input to the pixel element,    -   wherein the timing of application of the data signals is        selected in dependence on the signals on at least one of the two        inputs,    -   wherein a capacitive connection is provided between the gate of        at least one switching transistor and an output of the switching        transistor, and    -   wherein the timing is controlled such that the capacitive        connection reduces the required voltage swing in the data signal        between that required to turn on and turn off a switching        transistor.

This method can be used in driving of a liquid crystal display. In afirst mode, analogue pixel drive signals can be switched to each pixelof the display (normal mode) and in a second mode, the method of theinvention can be used for routing one of two pixel drive signals (brightor dark) on respective inputs to each pixel of the display (digital lowpower mode).

Examples of the invention will now be described in detail with referenceto the accompanying drawings, in which:

FIG. 1 shows schematically a known switching circuit for selecting oneof two inputs;

FIG. 2 shows an implementation of the circuit of FIG. 1;

FIGS. 3 and 4 show different waveforms for controlling the circuit ofFIG. 2;

FIG. 5 shows one example of a known pixel configuration for an activematrix liquid crystal display;

FIG. 6 shows a display device including row and column driver circuitry;

FIG. 7 shows a first example of switching circuit of the invention;

FIGS. 8 and 9 show different waveforms for controlling the circuit ofFIG. 7;

FIG. 10 shows a second example of switching circuit of the invention;

FIG. 11 shows a third example of switching circuit of the invention;

FIG. 12 shows a first example of circuit of the invention used within apixel of an active matrix display;

FIG. 13 shows a second example of circuit of the invention used within apixel of an active matrix display; and

FIG. 14 shows a third example of circuit of the invention used within apixel of an active matrix display.

FIG. 5 shows a conventional pixel configuration for an active matrixliquid crystal display. The display is arranged as an array of pixels inrows and columns. Each row of pixels shares a common row conductor 10,and each column of pixels shares a common column conductor 12. Eachpixel comprises a thin film transistor 14 and a liquid crystal cell 16arranged in series between the column conductor 12 and a commonelectrode 18. The transistor 14 is switched on and off by a signalprovided on the row conductor 10. The row conductor 10 is thus connectedto the gate 14 a of each transistor 14 of the associated row of pixels.Each pixel additionally comprises a storage capacitor 20 which isconnected at one end 22 to the next row electrode, to the preceding rowelectrode, or to a separate capacitor electrode. This capacitor 20stores a drive voltage so that a signal is maintained across the liquidcrystal cell 16 even after the transistor 14 has been turned off.

In order to drive the liquid crystal cell 16 to a desired voltage toobtain a required gray level (which may be simply black or white), anappropriate signal is provided on the column conductor 12 in synchronismwith a row address pulse on the row conductor 10. This row address pulseturns on the thin film transistor 14, thereby allowing the columnconductor 12 to charge the liquid crystal cell 16 to the desiredvoltage, and also to charge the storage capacitor 20 to the samevoltage. At the end of the row address pulse, the transistor 14 isturned off, and the storage capacitor 20 maintains a voltage across thecell 16 when other rows are being addressed. The storage capacitor 20reduces the effect of liquid crystal leakage and reduces the percentagevariation in the pixel capacitance caused by the voltage dependency ofthe liquid crystal cell capacitance.

The rows are addressed sequentially so that all rows are addressed inone frame period, and refreshed in subsequent frame periods.

As shown in FIG. 6, the row address signals are provided by row drivercircuitry 30, and the pixel drive signals are provided by column addresscircuitry 32, to the array 34 of display pixels.

In order to enable a sufficient current to be driven through the thinfilm transistor 14, which is implemented as an amorphous silicon orpolycrystalline silicon thin film device, a high gate voltage must beused. In particular, the period during which the transistor is turned onis approximately equal to the total frame period within which thedisplay must be refreshed, divided by the number of rows. The gatevoltage for the on-state and the off-state differ by approximately 12Volts for polysilicon displays in order to provide the required smallleakage current in the off-state, and sufficient current flow in theon-state to charge or discharge the liquid crystal cell 16 within theavailable time.

FIG. 7 shows a first switch arrangement in accordance with theinvention, in which the voltage swing on the signal required to drivethe circuit between the two possible states is reduced. Theimplementation of the switching circuit into an array device will bedescribed further below.

As shown, a capacitor, C_(B), is connected between data voltage node 40and the output signal node 43. The two switching transistors 50 are ofopposite polarity type. When the data voltage is applied to the datavoltage node 40 by means of a transfer switch 42, the input signals areheld at voltage levels which maximise the gate-source voltage present onthe TFT which is to be turned on. This implies that the signal connectedto the input of the n-type TFT, signal 1, should be at its lowestvoltage level and the signal at the input of the p-type TFT, signal 2,should be at its highest voltage level. The data voltage node is thenisolated from the source of data by the transfer switch 42 and the datavoltage is held on the capacitor C_(B). Any changes in the output signalvoltage are coupled onto the data voltage node thus maintaining thegate-source voltage of the device which is conducting. The advantage ofthis can be illustrated by considering the two sets of example waveformsused in the analysis above.

FIG. 8 shows how the waveforms of FIG. 3 can be modified to suit thepixel arrangement of FIG. 7, which uses the bootstrap capacitor C_(B). Anew waveform, “transfer data”, has been added. When this signal is high,the data voltage level is transferred to the data voltage node 40 fromthe data source. When the signal is low, the data voltage node 40 isisolated from the data source. This function can be achieved using a TFTswitch as indicated in FIG. 7. The effect of introducing the capacitorC_(B) into the switching circuit is to modify the voltage waveformappearing on the data voltage node. The data voltage required to switchon the n-type device can be minimised if the data voltage is transferredfrom the data source when the voltage present at the signal 1 input isat its minimum level. Thus, the second pulse in the “transfer data”waveform is timed to correspond to a trough in the “signal 1” waveform.

The required data voltage levels for switching the two transistors aresummarised in Table 3. TABLE 3 Data Required Equation for Values forRequired volt- Conditions for required data specified data age TFTswitching voltages conditions voltage V_(DH) n-type TFT on V_(DH) ≧ 0 +V_(non)   ≧4 V 4.5 V p-type TFT off V_(DH) ≧ 0.5 V_(DR) − V_(poff) ≧4.5V V_(DL) n-type TFT off V_(DL) ≦ 0 − V_(noff)   ≦0 V   0 V p-type TFT onV_(DL) ≦ 0.5 V_(DR) + V_(pon) ≦0.5 V

The switching conditions for the p-type device are unchanged from theprevious case when C_(B) was not present. However, the high data voltagelevel required to turn on the n-type transistor is now reduced. Signal 1is at 0V when the data voltage is transferred to the data voltage nodeand therefore a data voltage of V_(non) is sufficient to turn on then-type device. When the voltage applied to the signal 1 input changes toa level V_(DR) this change in voltage is coupled onto the data voltagenode by C_(B) since the data voltage node is now isolated from the datasource. The voltage on the gate of the TFTs increases to approximatelyV_(DH)+V_(DR) which will ensure that the n-type device remains in aconducting state in spite of the increased voltage at its source anddrain terminals. The consequence of this bootstrapping effect is thatthe high level data voltage required to switch the n-type device is only4V. This is less than the high level voltage required to maintain thep-type device in a non-conducting state and therefore for the specificvalues used in this example the minimum required high data voltage levelis 4.5V. In practice, the bootstrapping effect of C_(B) will not beperfect due to the presence of other capacitances at the data voltagenode. The effect of these capacitances will be to make the change in thevoltage on the gate of the transistor smaller than the change in voltageon the source. The gate-source voltage will therefore decrease as thesignal voltage increases and the transistor will become less conducting.This may necessitate the use of a somewhat higher data voltage than ispredicted by this simple analysis.

This example illustrates that by introducing the capacitor C_(B) intothe switching circuit and by transferring the data voltage to the datavoltage node when the signal voltage is at an optimum level and thenisolating that node, a substantial reduction in the required datavoltage range can be achieved, thus reducing the power consumption ofthe display.

FIG. 9 shows how the waveforms of FIG. 4 can be modified to suit thepixel arrangement of FIG. 7, which uses the bootstrap capacitor C_(B).The “transfer data” waveform again indicates the time when the datavoltage is transferred to the data voltage node. By transferring thedata voltage to the data voltage node when signal 1 is at its minimumlevel and signal 2 is at its maximum level it is possible to reduce thedifference between the high and low data voltage levels required toswitch the p-type and n-type TFTs. As in the previous example, theeffect of C_(B) is to couple changes in the output voltage onto the datavoltage node following the isolation of the data voltage node from thedata voltage source. In the case when the data voltage is initially atthe low level, V_(DL), when signal 2 goes to its minimum value, theoutput drive voltage falls to the same level and the capacitor C_(B)will couple this change in voltage onto the data voltage node. Thisensures that the p-type device remains in a conducting state. In thecase when the data voltage is initially at the high level, V_(DH), whensignal 1 goes to its maximum value the output drive voltage rises to thesame level and the capacitor C_(B) will couple this change in voltageonto the data voltage node ensuring that the n-type device remains in aconducting state. The data voltage requirements for the switchingcircuit including C_(B) are summarised in Table 4. TABLE 4 Data RequiredEquation for Values for Required volt- Conditions for required dataspecified data age TFT switching voltages conditions voltage V_(DH)n-type TFT on V_(DH) ≧ 0 + V_(non)   ≧4 V   4 V p-type TFT off V_(DH) ≧V_(DR) − V_(poff)  ≧3.5 V V_(DL) n-type TFT off V_(DL) ≦ 0 − V_(noff)  ≦0 V −0.5 V p-type TFT on V_(DL) ≦ V_(DR) + V_(pon) ≦−0.5 V

The required data voltage amplitude for the stated conditions isdetermined by the need to ensure that the n-type and p-type TFTs remainconducting when the input drive waveforms switch. The data signalamplitude is again substantially reduced by the introduction of thecapacitor C_(B) to a value of 4.5V.

It will be seen that this implementation of the invention provides amethod of selecting, routing or multiplexing signals using a network ofp-type or n-type thin film transistors. The bootstrapping technique, inwhich the output signal of the switching transistor is capacitivelycoupled onto its gate, allows relatively low data or control signalvoltages to be used to control the transistors. The correct operation ofthe circuit requires some knowledge of the signal characteristics sinceit is preferable to transfer the control data to the transistors whenthe signal voltages that they are passing are at their maximum (mostpositive) or minimum (most negative) voltage level for p-type and n-typedevices respectively. This approach minimises the voltage range of thesignals used to control the switches.

If the signal voltage passed by a TFT has a minimum level of V_(min) anda maximum level of V_(max) then the data or control voltage levelsrequired to switch the device using a conventional approach and theproposed bootstrapped approach are as indicated in Table 5 for an n-typedevice and Table 6 for a p-type device. It is assumed that the ratio ofthe bootstrapping capacitor C_(B) to the total capacitance of the datavoltage node is equal to k_(B). TABLE 5 Required Data voltages Equationsfor data Data Conditions for without voltages with voltage TFT switchingbootstrapping bootstrapping High n-type TFT on V_(DH) ≧ V_(max) +V_(non) V_(DH) ≧ V_(max) + V_(non) − k_(B)(V_(max) − V_(min)) level Lown-type TFT off V_(DL ≦ V) _(min) − V_(noff) V_(DL) ≦ V_(min) − V_(noff)level

TABLE 6 Required Data voltages Equations for data Data Conditions forwithout voltages with voltage TFT switching bootstrapping bootstrappingLow p-type TFT on V_(DL) ≦ V_(min) + V_(pon) V_(DL) ≦ V_(min) +V_(pon) + k_(B)(V_(max) − V_(min)) level High p-type TFT off V_(DH) ≧V_(max) − V_(poff) V_(DH) ≧ V_(max) − V_(poff) level

The examples above show that the bootstrapping technique could beapplied to a one of two signal selection function. However, theinvention can also be applied to other arrangements of switchingtransistors.

FIG. 10 shows an example of a one of four selection circuit. The controlsignals “data 1” to “data 4” are generated in such a way as to turn onone of the four switching transistors 50. A combination of p-type andn-type TFT switches can be used as shown in FIG. 10 although transistorsof the same type may be used.

FIG. 11 is an example of a two bit voltage selector. This makes use ofseries-connected switching transistors to provide a decoding and signalswitching function.

The switching circuit has 4 inputs (“signal 0” to “signal 3”), and theselection of one of these is by a two bit control signal D0, D1. Thecircuit has two layer 52, 54. The first layer 52 has first to fourthswitching transistors 50 a-50 d connected between a respective one ofthe inputs and one of two intermediate outputs 56, 58. The first layer52 is controlled by one of the bits D0 of the two bit word, and this bitdetermines which two of the signal inputs are routed to the intermediateoutputs. The second layer 54 selectively routes one of the intermediateoutputs as the output signal, and is controlled by the other bit D1 ofthe control signal. The circuit of FIG. 11 is thus formed as a cascadeof one-of-two selection circuits.

The circuit of the invention can be used in numerous applications.Essentially, the application requires the input signal waveforms to beknown, so that the timing of the “transfer data” signal can be selectedto take advantage of the capacitive coupling of the bootstrapcapacitors. The invention enables reduced switching voltage levels, andcan be used in multiplexer circuits as well as a range of array-typecircuit configurations.

One particularly advantageous use of the circuit of the invention is inactive matrix display devices, in particular integrated into the pixeldesign. The circuit can then provide selection between two brightnesslevels for example for a low power binary display mode. The invention isalso particularly suited to displays with integrated memory capability,as described below.

An example of a pixel circuit for an AMLCD which makes use of thecircuit of the invention is shown in FIG. 12. The pixel includes thestandard pixel circuitry of FIG. 5, and the same reference numerals areused for the same components as in FIG. 5. These components enable thepixel to be operated in the normal analogue drive mode. This may beconsidered as a first mode of operation.

The pixel also includes a switching circuit 60 corresponding to thatdescribed with reference to FIG. 7. Again, the same reference numeralsare used for the same components as in FIG. 7. This switching circuit 60enables selection between two drive voltage levels “Vdrive1” and“Vdrive2” shared between all pixels. The transfer switch 42, whichcontrols the timing of application of the data signal to the gates ofthe switching transistors, is controlled by a “Data_address” line, whichis shared between rows of pixels. The selected drive signal is coupledbetween the common output 62 of the switching circuit 60 and the liquidcrystal cell 16 by a first selection switch 64, which is controlled by a“Pixel_refresh” line, the function of which will be described below. Thetransistor 14 may be considered as a second transfer switch, and thesetwo transfer switches dictate which part of the pixel (either theanalogue or the binary part) supplies the drive signal to the liquidcrystal cell 16.

The pixel can, thus, be operated in two modes. In the first analoguemode, the Pixel_refresh electrode is held at a low level so that thedisplay element is isolated from the switching circuit 60 by the firsttransfer switch 64. In a second operating mode, a digital data signal isapplied to the column 12. One bit of data is transferred from the columnelectrode 12 to the data voltage node 40 by applying a positive goingpulse to the Data_address line. This turns on the transfer switch 42 andallows the bootstrapping capacitor C_(B) to be charged.

The bootstrapping capacitor can also act as a capacitance on which thedigital data is stored within the pixel. As discussed above, this datatransfer is carried out when the signal Vdrive1 is at its minimumvoltage level and the signal Vdrive 2 is at its maximum voltage level(as explained with reference to FIG. 9), in order to minimise the rangeof the digital data voltage that is required to switch the switchingtransistors 50. After the data has been transferred to the data voltagenode, one of the switching transistors 50 will be in a conducting state,and the other device will be in a non-conducting state. Therefore one ofthe two signals, Vdrive1 and Vdrive2, appears at the output 62 of theswitching circuit.

This drive signal is periodically applied to the display element, forexample every 20 ms, by applying a positive going pulse to thePixel_refresh line and turning on the first transfer switch 64.

As mentioned above, the bootstrapping capacitor can function as anintegrated memory element. In particular, the capacitor will be chargedto different levels depending which of the two signal inputs is switchedto the common output. Integrated memory capability has been proposed, asa significant fraction of the power consumption of an active matrixdisplay device is associated with transferring video information fromthe video signal source to the pixels of the display device. Thiscomponent of the power can be reduced if the pixels of the displaydevice are able to store the video information for an indefinite periodof time. In this case the addressing of the pixels with fresh videoinformation can be suspended when no change to the display output(brightness) state of pixels is required.

Incorporating memory into the pixels of an active matrix display devicecan thus reduce power when a static image display is permitted becausedata need only be sent to the display pixels when the image changes andless power is, therefore, consumed in external circuits and in drivingthe capacitance associated with connections to the display pixels. Thepixel circuit of the invention enables a black and white image to bedisplayed in this low power mode with reduced addressing voltage levels.

When the capacitor is used as a memory element, the digital data whichis held on C_(B) must be refreshed periodically since switch 64 andC_(B) effectively form a one bit dynamic memory cell. This refreshingcan be achieved by transferring data from an external memory via thecolumn drive circuit and the column electrodes of the display.Alternatively, it might be achieved by reading out the stored data ontothe column electrode via the transistors 14 and 64 and making use of theswitching circuit formed by transistors 50 to buffer the data signal. Ineither case, the reduction in the amplitude of the digital data signalsresulting from the bootstrapping technique will reduce the amplitude ofthe digital signals which must be applied to the columns of the display,and this in turn will reduce the power consumption of the display.

The frequency with which the digital data must be refreshed depends onthe value of the capacitor C_(B) and the leakage current through thetransfer transistor 42. A frequency in the range 5 Hz to 30 Hz mighttypically be achievable.

In the examples above, the switching circuit is used to select one of atleast two drive voltages and provide these to a common output. Thebootstrapping technique can however be applied to an AMLCD pixel circuitwith only one drive voltage input being switched using the switchingarrangement of the invention. FIG. 13 shows a modification to FIG. 12for this purpose. In FIG. 13, the same reference numerals are used as inFIG. 12 for the same components.

The pixel circuit of FIG. 13 can be operated in a similar manner to thecircuit of FIG. 12 but it has only one switching transistor 50controlled by the data stored on the bootstrap capacitor CB. When thecolumn data voltage is high, and is routed by the transfer switch 42 tothe switching transistor 50, the switching transistor 50 is turned on.When the pixel_refresh line is taken high, the pixel is charged to thelevel of Vdrive1 through the transfer switch 64.

When the column data voltage is low, the switching transistor 50 isturned off, and when the pixel_refresh line is taken high the pixelvoltage remains unchanged. The second pixel drive voltage level that isrequired in order to switch the pixel into a dark state or a light statecan be applied to the pixel by using precharging of the pixelcapacitance. The pixel is precharged by applying a precharge voltage(for example similar to Vdrive2 in the pixel circuit example in FIG. 12)to the columns of the display and briefly turning on the pixel addresstransistor 14 before the transfer switch 64. In this way, if the columndata voltage is high then the resulting voltage on the pixel electrodewill be Vdrive1 but if the column data voltage is low then the resultingvoltage on the pixel electrode will be the precharge voltage (Vdrive2).

In this way, a precharge of Vdrive2 is applied to the pixel just beforethe pixel is addressed. If the column data voltage is high, this isoverridden whereas if the column voltage is low, Vdrive2 stays on thepixel. During the pixel address phase, the transistor 14 is turned off.

In the circuit of FIG. 13, transistor 50 acts as one of the switchingtransistors of the digital switching circuit and transistor 14 acts asthe other. They do not share an immediate common output, but they areeffectively connected between each input and the LC cell 16 which isthus effectively the common output. The claims should be construedaccordingly.

In this case, the timing of application of the data signal still reducesthe required voltage swing of the column data, by timing theData_address pulse with the minimum voltage of the Vdrive1 signal, whichmay correspond to signal 1 in FIG. 8. Similarly, the precharge voltageapplied to the column for transfer to the pixel through the pixeladdress transistor 14 may correspond to signal 2 of FIG. 8.

In the examples above, the bootstrap capacitor is connected between thegate of each switching transistor and a common output. However, theremay be some situations when the outputs of the switching transistorswhich select the input signal are not connected directly to a commonoutput node. The pixel circuit of FIG. 14 contains a digital to analogueconverter. This operates in a similar way to the pixel circuit of FIG.13 in that the pixel is precharged to a certain voltage using transistorT1 but then the pixel voltage can be changed by coupling a voltage stepfrom Vdrive1 onto the pixel via the converter capacitors C_(C).

The magnitude of the voltage coupled onto the pixel will depend on thedata voltages on the capacitors C_(B). Note that the outputs of theswitching transistors are connected to a common output node but via theadditional series-connected capacitiors. These provide the digital toanalogue conversion from the digital word on the “Data” lines.

The techniques underlying the invention could be applied very widely, toany situation where it is desirable to use a combination of p-typetransistors, n-type transistors or a combination of both to produce acircuit for routing or selecting signals based on the state of digitalcontrol or data signals. As outlined above, the technique is ofparticular interest for use in displays where dynamic memory integratedwithin the pixel is used to control its brightness.

The terms “row” and “column” are somewhat arbitrary in the descriptionand claims. These terms are intended to clarify that there is an arrayof elements with orthogonal lines of elements sharing commonconnections. Although a row is normally considered to run from side toside of a display and a column to run from top to bottom, the use ofthese terms is not intended to be limiting in this respect.

Other features of the invention will be apparent to those skilled in theart.

1. A device comprising an array of pixels, each pixel including a pixelelement and being associated with a switching circuit, wherein theswitching circuit is for selectively routing one of at least two inputsto the pixel element, comprising at least first and second switchingtransistors connected between a respective one of the at least twoinputs and the pixel element, wherein each switching transistor iscontrolled by a data signal applied to the gate of the transistor,wherein the data signal for each switching transistor is routed to thegate of the switching transistor with predetermined timing determined independence on the data waveform of at least one of the inputs, andwherein a capacitive connection is provided between the gate of at leastone of the switching transistors and an output of the switchingtransistor.
 2. A device as claimed in claim 1, wherein the data signalfor each switching transistor is routed to the gate of the switchingtransistor by a transfer switch which controls the timing of applicationof the data signal for each switching transistor, and wherein acapacitive connection is provided between the gate of each switchingtransistor and the output of each switching transistor.
 3. A device asclaimed in claim 2, wherein a capacitive connection is provided betweenthe gate of each switching transistor and an output of the switchingcircuit.
 4. A device as claimed in any preceding claim, wherein thegates of the first and second switching transistors are connectedtogether and the capacitive connection comprises a capacitor connectedbetween the gates and an output of the switching circuit.
 5. A device asclaimed in claim 4, wherein the first switching transistor is an n-typetransistor and the second switching transistor is a p-type transistor.6. A device as claimed in claim 1, wherein the capacitive connectioncomprises a respective capacitor connected between the gate of eachswitching transistor and an output of the switching circuit.
 7. A deviceas claimed in claim 6, comprising n inputs, where n is greater than 2,and comprising first to nth switching transistors connected between arespective one of the n inputs and the pixel element, and wherein thedata signals for each switching transistor are selected such that anindividual one of the switching transistors is turned on to route therespective input to the pixel element.
 8. A device as claimed in claim7, wherein at least one of the switching transistors is n-type and atleast one of the switching transistors in p-type.
 9. A device as claimedin claim 7, wherein all switching transistors are of the same polaritytype.
 10. A device as claimed in claim 6, comprising n inputs, andcomprising first to nth switching transistors connected between arespective one of the n inputs and one of two intermediate outputs, andwherein the data signals for each switching transistor are selected suchthat half of the switching transistors are turned on to route a firstselected input to one intermediate output and to route a second selectedinput to the other intermediate output.
 11. A device as claimed in claim10, further comprising a switching circuit for selectively routing oneof the intermediate outputs to the pixel element.
 12. A device asclaimed in claim 1 comprising an active matrix liquid crystal displaydevice in which the pixel elements comprise liquid crystal cells, eachpixel comprising the switching circuit for routing one of two voltagedrive levels to the pixel element.
 13. A device as claimed in claim 12,further comprising: a first selection switch between the common outputof the switching circuit and the liquid crystal cell of the pixel; and asecond selection switch between an analogue pixel data line and theliquid crystal cell of the pixel.
 14. A device as claimed in claim 13,wherein the two voltage drive levels comprise voltages for driving theliquid crystal cell to a black and a white state.
 15. A device asclaimed in claim 13, wherein the control signal for selecting which oneof the two voltage drive levels is to be routed to the pixel element isprovided on the analogue pixel data line.
 16. A device as claimed inclaim 15, wherein the data signal for each switching transistor isrouted to the gate of the switching transistor by a transfer switchwhich controls the timing of application of the data signal for eachswitching transistors, and wherein a capacitive connection is providedbetween the gate of each switching transistor and the output of eachswitching transistor, and wherein the transfer switch is providedbetween the analogue pixel data line and the gates of the first andsecond switching transistors.
 17. A device as claimed in claim 12,further comprising: a first selection switch between the output of theat least one of the switching transistors and the liquid crystal cell ofthe pixel; and a second selection switch between an analogue pixel dataline and the liquid crystal cell of the pixel.
 18. A device as claimedin claim 17, wherein the second selection switch comprises the other ofthe first and second switching transistors.
 19. A device as claimed inclaim 18, wherein in a first mode, the second selection switch providesone of two digital pixel signals from the analogue pixel data line tothe liquid crystal cell, and in a second mode the second selectionswitch provides an analogue pixel signal from the analogue pixel dataline to the liquid crystal cell.
 20. A method of routing one of at leasttwo inputs to a pixel element within a pixel of a device comprising anarray of pixels, the method comprising: applying data signals to thegates of at least first and second switching transistors connectedbetween a respective one of the at least two inputs and the pixelelement to turn on a selected one of the first and second switchingtransistors and turn off the other of the first and second switchingtransistors, thereby routing the respective input to the pixel element,wherein the timing of application of the data signals is selected independence on the signals on at least one of the two inputs, wherein acapacitive connection is provided between the gate of at least oneswitching transistor and an output of the switching transistor, andwherein the timing is controlled such that the capacitive connectionreduces the required voltage swing in the data signal between thatrequired to turn on and turn off a switching transistor.
 21. A method ofdriving a liquid crystal display, comprising: in a first mode, switchinganalogue pixel drive signals to each pixel of the display; and in asecond mode, routing one of two pixel drive signals on respective inputsto each pixel of the display, the routing for each pixel in the secondmode using the method of claim 20.